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82708 ms pc/91002as (ot) no.7257-1/11 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. lb11872h overview the lb11872h is a three-phase brushless motor driver developed for driving the motors used for the polygonal mirror in laser printers and similar applications. it can implement, with a single ic chip, all the circuits required for polygonal mirro r drive, including speed control and driver functions. the lb11872h can implement motor drive within minimal drive noise due to its use of current linear drive. features ? three-phase bipolar current linear drive + midpoint control circuit. ? pll speed control circuit. ? speed is controlled by an external clock signal. ? supports hall fg operation. ? built-in output saturation prevention circuit. ? phase lock detection output (with masking function). ? includes current limiter, thermal protection, rotor constrai nt protection, and low-voltage protection circuits on chip. ? on-chip output diodes. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc max 30 v output current i o max t 500ms 1.2 a pd max1 independent ic 0.8 w allowable power dissipation pd max2 *with specified substrate 2.0 w operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c ? when mounted on the specified printed circuit board : 114.3mm 76.1mm 1.6mm, glass epoxy monolithic digital ic for polygonal mirror motors three-phase brushless motor driver orderin g numbe r : en7257b
lb11872h no.7257-2/11 allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc 10 to 28 v 6.3 v regulator-voltage output current ireg 0 to -20 ma ld pin applied voltage vld 0 to 28 v ld pin output current ild 0 to 15 ma fgs pin applied voltage vfg 0 to 28 v fgs pin output current ifg 0 to 10 ma electrical characteristics at ta = 25 c, v cc = vm = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 stop mode 5 7 ma supply current 2 i cc 2 start mode 17 22 ma output saturation voltages vagc = 3.5v source (1) vsat1-1 i o = 0.5a, rf = 0 1.7 2.2 v source (2) vsat1-2 i o = 1.0a, rf = 0 2.0 2.7 v sink (1) vsat2-1 i o = 0.5a, rf = 0 0.4 0.9 v sink (2) vsat2-2 i o = 1.0a, rf = 0 1.0 1.7 v output leakage current i o (leak) v cc = 28v 100 a 6.3v regulator-voltage output output voltage vreg 5.90 6.25 6.60 v voltage regulation vreg1 v cc = 9.5 to 28v 50 100 mv load regulation vreg2 iload = -5 to -20ma 10 60 mv temperature coefficient vreg3 design target value* 1 0 mv/ c hall amplifier block input bias current ib (ha) differential input : 50mvp-p 2 10 a differential input voltage range vh in sin wave input 50 *600 mvp-p common-phase input voltage range vicm differential input : 50mvp-p 2.0 v cc -2.5 v input offset voltage vioh design target value* 1 -20 20 mv fg amplifier and schmitt block (in1) input amplifier gain gfg 5 times input hysteresis (high to low) vshl 0 mv input hysteresis (low to high) vslh -10 mv hysteresis width vfgl input conversion 4 7 12 mv low-voltage protection circuit operating voltage vsd 8.4 8.8 9.2 v hysteresis width vsd 0.2 0.4 0.6 v thermal protection circuit thermal shutdown operating temperature tsd design target value* 1 (junction temperature) 150 180 c hysteresis width tsd design target value* 1 (junction temperature) 40 c current limiter operation acceleration limit voltage vrf1 0.53 0.59 0.65 v deceleration limit voltage vrf2 0.32 0.37 0.42 v error amplifier input offset voltage vio (er) design target value* 1 -10 10 mv input bias current ib (er) -1 1 a high-level output voltage v oh (er) i oh = -500 a vreg-1.2 vreg-0.9 v low-level output voltage v ol (er) i ol = 500 a 0.9 1.2 v dc bias level vb (er) -5% 1/2vreg 5% v note* : since kickback can occur in the output waveform if th e hall input amplitude is too large, the hall input. amplitudes sh ould be held to under 350mvp-p. * 1 : this parameter is a design target value and is not measured. continued on next page.
lb11872h no.7257-3/11 continued from preceding page. ratings parameter symbol conditions min typ max unit phase comparator output high-level output voltage vpdh i oh = -100 a vreg-0.2 vreg-0.1 v low-level output voltage vpdl i ol = 100 a 0.2 0.3 v output source current ipd + vpd = vreg/2 -500 a output sink current ipd - vpd = vreg/2 1.5 ma lock detection output output saturation voltage vld (sat) ild = 10ma 0.15 0.5 v output leakage current ild (leak) vld = 28v 10 a fg output output saturation voltage vfg (sat) ifg = 5ma 0.15 0.5 v output leakage current ifg (leak) vfg = 28v 10 a drive block dead zone width vdz with the phase is locked 50 100 300 mv output idling voltage vid 6 mv forward gain 1 gdf+1 with phas e locked 0.4 0.5 0.6 times forward gain 2 gdf+2 with phase unlocked 0.8 1.0 1.2 times reverse gain 1 gdf-1 with phase locked -0.6 -0.5 -0.4 times reverse gain 2 gdf-2 with phase unlocked -0.8 -1.0 -1.2 times acceleration command voltage vsta 5.0 5.6 v deceleration command voltage vsto 0.8 1.5 v forward limiter voltage vl1 rf = 22 0.53 0.59 0.65 v reverse limiter voltage vl2 rf = 22 0.32 0.37 0.42 v csd oscillator circuit oscillation frequency f osc c = 0.022 f 31 hz high-level pin voltage v csdh 4.3 4.8 5.3 v low-level pin voltage v csdl 0.75 1.15 1.55 v external capacitor charge and discharge current i chg 35 7 a lock detection delay count csdct1 7 clock cutoff protection operating count csdct2 2 lock protection count csdct3 31 initial reset voltage v res 0.60 0.80 v clock input block external input frequency f clk 400 10000 hz high-level input voltage v ih (clk) design target value* 1 2.0 vreg v low-level input voltage v il (clk) design target value* 1 0 1.0v input open voltage v io (clk) 2.7 3.0 3.3 v hysteresis width v is (clk) design target value* 1 0.1 0.2 0.3 v high-level input current i ih (clk) v (clk) = vreg 140 185 a low-level input current i il (clk) v (clk) = 0v -185 -140 a s/s pin high-level input voltage v ih (s/s) 2.0 vreg v low-level input voltage v il (s/s) 0 1.0 v input open voltage v io (s/s) 2.7 3.0 3.3 v hysteresis width v is (s/s) 0.1 0.2 0.3 v high-level input current i ih (s/s) v (s/s) = vreg 140 185 a low-level input current i il (s/s) v (s/s) = 0v -185 -140 a * 1 : this parameter is a design target value and is not measured.
lb11872h no.7257-4/11 package dimensions unit : mm (typ) 3233b pin assignment truth table out1 to out3 (h : source, l : sink) in1 in2 in3 out1 out2 out3 h l h l h m h l l l m h h h l m l h l h l h l m l h h h m l l l h m h l for in1 to in3, ?h? means that in + is greater than in - , and ?l? means in - is greater than in + . for out1 to out3, ?h? means the output is a source, and ?l? means that it is a sink. sanyo : hsop28h(375mil) 15.2 (6.2) 0.3 7.9 (4.9) 10.5 2.7 0.8 2.0 (0.8) 1 14 15 28 0.65 0.25 2.45max 0.1 (2.25) heat spreader pd max ? ta 0 1.2 1.6 2.0 0.8 0.4 2.4 ? 20 80 60 20 40 0 100 1.12 0.45 independent ic ambient temperature, ta ? c allowable power dissipation, pd max ? w specified board : 114.3 76.1 1.6mm 3 glass epoxy nc 12 13 14 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 in2 + in2 - in1 + in1 - in3 + in3 - agc mn nc nc csd nc fg out3 out2 out1 rf sub v cc vreg fc eo ei pd ld clk s/s gnd gnd hsop28h lb11872h top view
lb11872h no.7257-5/11 block diagram agc mn fg vreg fc eo ei pd ld clk csd ld fg s/s in1 in2 in3 15 21 18 19 20 16 22 12 17 14 9 3 4 5 6 7 2 frame 24 25 23 gnd rf 28 8 26 out3 out2 out1 6.3vreg pll v-amp tsd lvsd lock det agc hall amp & matrix ocl output ld pd osc clock det restrict det filter fg reset 5 sub 27 v cc v cc s/s + + - + - + - + - clk
lb11872h no.7257-6/11 pin functions pin no. pin name function equivalent circuit 2 3 4 5 6 7 in2 + in2 - in1 + in1 - in3 + in3 - hall effect sensor signal inputs. these inputs are high when in + is greater than in- and low when in- is greater than in + . insert capacitors between the in + and in? pins to reduce noise. an amplitude of over 50mvp-p and under 350mvp-p is desirable for the hall input signals. kickback can occur in the output waveform if the hall input amplitude is over 350mvp-p. 300 300 2 4 6 3 5 7 v cc 8 agc agc amplifier frequency characteristics correction. insert a capacitor (about 0.022 f) between this pin and ground. 300 8 vreg 9 mn monitor pin. this pin should be left open in normal operation. 12 csd used for both initial reset pulse generation and as the reference time for constraint protection circuits. insert a capacitor between this pin and ground. vreg 12 300 14 fg fg pulse output. this is an open-collector output. vreg 14 15 s/s start/stop control. low : start 0 to 1.0v high : stop 2.0v to vreg this pin goes to the high level when open. vreg 33k 5k 15 30k continued on next page.
lb11872h no.7257-7/11 continued from preceding page. pin no. pin name function equivalent circuit 16 clk clock input. low : 0 to 1.0v high : 2.0v to vreg this pin goes to the high level when open. vreg 33k 5k 16 30k 17 ld phase locked state detection output. this output goes to the on state when the pll locked state is detected. this is an open-collector output. vreg 17 18 pd phase comparator output (pll output). this pin output the phase error as a pulse signal with varying duty.the output current increases as the duty becomes smaller. vreg 18 19 ei error amplifier in put pin. vreg 300 19 20 eo error amplifier output pin. the output current increa ses when this output is high. vreg 20 300 40k continued on next page.
lb11872h no.7257-8/11 continued from preceding page. pin no. pin name function equivalent circuit 21 fc control amplifier frequency correction. inserting a capacitor (about 5600pf) between this pin and ground will stop closed loop oscillation in the current control syst em. the output current response characteristics will be degraded if the capacitor is too large. 21 vreg 22 vreg stabilized power supply (6.3v) insert a capacitor (about 0.1 f) between this pin and ground for stabilization. 22 v cc 23 v cc power supply. 24 sub sub pin. connect this pin to ground. 25 rf output current detection. insert low-valued resistors (rf) between these pins and ground. the output current will be limited to the value set by the equation i out = v l /rf. 26 27 28 out1 out2 out3 motor drive outputs. if the output oscillates, insert a capacitor (about 0.1 f) between this pin and ground. 26 27 28 300 vreg v cc 25 1 10 11 13 nc no connection (nc) pins. these pins may be used for wiring connections. frame gnd ground.
lb11872h no.7257-9/11 lb11920 description 1. speed control circuit this ic adopts a pll speed control technique and provides stable motor operation with high precision and low jitter. this pll circuit compares the phase erro r at the edges of the clk signal (fa lling edges) and fg signal (rising edges (low to high transitions) on the in1 input), and the ic uses the detected error to control the motor speed. during this control operation, the fg servo fre quency will be the same as the clk frequency. f fg (servo) = f clk 2. output drive circuit to minimize motor noise, this ic adopts three-phase full-wave current linear drive. this ic also adopts a midpoint control technique to prevent aso destruction of the output transistors. reverse torque braking is used during motor deceleration during speed switchi ng and lock pull-in. in stop mode, the drive is cut and the motor is left in the free-running state. since the output block may oscillate depending on the motor actually used, capacitors (about 0.1 f) must be inserted between the out pins and ground. 3. hall input signals this ic includes an agc circuit that minimizes the influence on the output of changes in the hall signal input amplitudes due to the motor used. however, note that if there are discrepancies in the input amplitudes between the individual phases, discrepancies in the output phase switching timing may occur. an amplitude (differential) of at leas t 50mvp-p is required in the hall input signals. however, if the input amplitude exceeds 350mvp-p, the agc circuit control range will be exceeded and kickback may occur in the output. if hall signal input frequencies in excess of 1khz (the freq uency in a single hall input ph ase) are used, internal ic heating during startup and certain other times (that is, when the output transistors are saturated) may increase. reducing the number of magnetic poles ca n be effective in dealing with problem. the in1 hall signal is used as the fg signal for speed cont rol internally to the ic. since noise can easily become a problem, a capacitor must be inserted across this input. ho wever, since this could result in differences between the signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases. although v cc can be used as the hall element bias power supp ly, using vreg can reduce the chances of problems occurring during noise testing and at other times. if vreg is used, since there is no longer any need to be concerned with the upper limit of the hall amplifier common-mode inpu t voltage range, bias setting resistors may be used only on the low side. 4. power saving circuit this ic goes into a power sa ving state that reduces the cu rrent drain in the stop state. the power saving state is implemented by removing the bias current from most of the circuits in the ic. however, the 6.3v regulator output is provided in the power saving state. 5. reference clock care must be taken to assure that no chattering or other noise is present on the externally input clock signal. although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. this ic includes an internal clock cutoff protection circuit. if a signal with a frequency below that given by the formula below is input, the ic will not perform normal contro l, but rather will operate in intermittent drive mode. f (hz) 0.64 c csd c csd ( f) : the capacitor inserted be tween the csd pin and ground. when a capacitor of 0.022 f is used, the frequency will be about 29hz. if the ic is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat and then motor drive will be shut off. after the motor stops and the rotor constraint protection time elapses, drive will not be restarted, even if the clock signal is th en reapplied. however, drive will restart if the clock signal is reapplied before the rotor constraint protection time elapses.
lb11872h no.7257-10/11 6. rotor constraint protection circuit this ic provides a rotor constraint protection circuit to protect the ic itself and the motor when the motor is constrained physically, i.e. prevented from turning. if the fg signal (edg es of one type (rising or falling edges) on the in1 signal) does not switch within a fixed time, output drive will be turned off. the time constant is determined by the capacitor connected to the csd pin. < time constant (in seconds) > 30.5 1.57 c csd ( f) if a 0.02 f capacitor is used, the protection time will be about 1.05 seconds. to clear the rotor constraint pr otection state, the ic must be set to the stop ped state or the power must be turned off and reapplied. if there is noise present on the fg signal during the constraint time, the rotor constraint protection circuit may not operate normally. 7. phase lock signal (1) phase lock range since this ic does not include a counter or similar functio nality in the speed control system, the speed error range in the phase locked state cannot be determined solely by ic characteristics. (this is because the acceleration of the changes in the fg frequency influences the range.) when it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. since speed errors occur easily in states where the fg acceleration is la rge, it is thought th at the speed errors will be the larg est during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) masking function for the phase lock state signal a stable lock signal can be provided by masking the shor t-term low-level signals due to hunting during lock pull-in. however, this results in the lock state signal output being delayed by the masking time. the masking time is determined by the capac itor inserted between the csd pin and ground. < masking time (seconds) > 6.5 1.57 c csd ( f) when a 0.022 f capacitor is used, the masking time will be about 2 25ms. in cases where complete masking is required, a masking time with fully adequate margin must be used. 8. initial reset to initially reset the logic circuits in start mode, the ic goes to the reset state when the csd pin voltage goes to zero until it reaches 0.63v. drive output starts after the reset st ate is cleared. the reset time can be calculated to a good approximation using the following formula. < reset time (seconds) > 0.13 c csd ( f) a reset time of over 100 s is required. 9. current limiter circuit the current limit value is determined by the resistor rf inserted between the rf pin and ground. i lim = v l /rf v l = 0.59v (typical) (during acceleration) an d 0.37v (typical) (d uring deceleration) 10. power supply stabilization an adequately large capacitor mu st be inserted between the v cc pin and ground for power supply stabilization. if diodes are inserted in the power supply lines to prevent dest ruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even mo re easily disrupted, and even larger capacitors must be used. if high-frequency noise is a problem , a ceramic capacito r of about 0.1 f must also be inserted in parallel. 11. vreg stabilization a capacitor of at least 0.1 f must be used to stabilize the vreg voltage , which is the control circuit power supply. the capacitor must be connected as close as possible to the pins. 12. error amplifier external component values to prevent adverse influence from noise, the error amplifier external components must be located as close to the ic as possible.
lb11872h ps no.7257-11/11 13. frame pin and heat sink area the frame pin and the heat sink area function as the control circuit ground terminal. it is desirable that this ground line and the rf resistor ground line be grounded at a single point at the ground for the electrolytic capacitor. thermal dissipation can be improved signif icantly by tightly bonding the metallic surface of the back of the ic package to the pcb with, for example, a solder with good thermal conductivity. 14. csd pin the capacitor connected to the csd pin influences several oper ational aspects of this ic, including the rotor constraint protection time and the phase lo ck signal mask time. the following are possible ways of determining the value of this capacitor. (1) if removing chattering from the phase lock state signal is most important : select a capacitance that can assure an adequate mask time. (2) if startup time is more important than chattering : select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that there are no problems with the clock cutoff protection circuit and initial reset time. operation of the rotor constraint protection circuit may hi nder the study of motor characteristics in the uncontrolled state. it is possible to only operate the initial reset functi on and not operate the rotor constraint protection circuit by inserting a resistor (about 390k ) in parallel with the capacitor between the csd pin and ground. 15. fc pin the capacitor connected to the fc pin is required for current limiter loop phase compensation. if the value is too low, the output will oscillate. if the value is too large, it will be eas ier for currents in excess of the limit value to flow durin g the current limit time (time before the ci rcuit operates) in states where the output is saturated. (this is because the control response characteristics become worse.) 16. agc pin a capacitance that allows a certain amount of smoothing of the agc pin voltage in the motor speed range used must be selected for the capacitor conn ected to the agc pin. it is also desirabl e to use a capacitance that allows the agc voltage to reach an essentially stabilized voltage before the initial reset is cleared. (if the capacitance is too large, the rate of change of the agc voltage will become slower.) sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of august, 2008. specifications and information herein are subject to change without notice.

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